1. Field
Example embodiments relate to a semiconductor device. More particularly, example embodiments relate to a semiconductor device having a wiring structure.
2. Description of the Related Art
Recently, as the integration degree of a semiconductor device increases, a line width and a pitch of wiring patterns in the semiconductor device have decreased. Accordingly, a parasitic capacitance between the neighboring wiring patterns may increase thereby to cause RC delay and a reduction of an operational speed of the semiconductor device.